Power supply sequencing distributed among multiple devices with linked operation

ABSTRACT

A system and method is provided to accomplish distributed power sequencing function of a large electronics system with minimum number of signals in the sequencing network without compromising the flexibility and expandability. In one embodiment of the invention, the power sequencing function is accomplished with two signals of the sequencing network: power_on/power_off signal and SEQ_LINK signal. The power_on/power_off signal controls whether the sequencing is in power_on mode for turning on power to multiple devices in a predetermined sequence or power_off mode for for turning off power to multiple devices in a reverse sequence. The SEQ_LINK signal controls when the sequence counters, located in each participating device, are allowed to count to the subsequent state. Each sequencing logic circuit of these participating devices responds to a predetermined sequence position to enable the power on or power off of the power supply it controls.

CROSS REFERENCE TO RELATED APPLICATIONS

This invention is a continuation of and claims the benefit of priorityfrom U.S. patent application Ser. No. 11/119,307, filed Apr. 28, 2005,entitled “Power Supply Sequencing Distributed Among Multiple Deviceswith Linked Operation,” the disclosure of which is hereby incorporatedherein by reference.

BACKGROUND

1. Field

The invention relates in general to electronics systems and, inparticular to power management in electronics systems.

2. Related Art

Electronics systems are frequently comprised of multiple devices. It isoften advantageous to have an automatic system for turning on power orturning off power to multiple devices in a predetermined sequence forfunctional purposes or for reliability considerations. Conventionalpower sequencing circuits employ centralized control circuitry to turnon power for a first device, then waits for a specified amount ofprogrammed delay time before it turns on power for a second device andso on. Power off sequencing is done in the same manner typically in areverse order to the power on sequencing. Each device requires its ownconnection with the centralized controller making system reconfigurationor expansion cumbersome. In a distributed power sequencing approach,each device includes sequencing logic circuit to participate inproviding power sequencing function with the centralized controlcircuitry in a coordinated manner. The communications among the centralcontrol circuitry and each of the sequencing logic circuit on theseparticipating devices are accomplished via signals in a sequencingnetwork. The flexibility and expandability of the power sequencingfunction to support reconfiguration or expansion of the electronicssystem is limited by available signals in the sequencing network.Accordingly, there is a need for an improved system and method toaccomplish the power sequencing function of a large electronics systemwith minimum number of signals in the sequencing network withoutcompromising the flexibility and expandability.

SUMMARY

This invention enables seamless distribution of the power sequencingfunction, normally limited by available signals of a sequencing networkin an electronics system, over multiple devices for expanding thefunctional capacity of the sequencing network for the system. In oneembodiment of the invention, the power sequencing function isaccomplished with two signals of the sequencing network:power_on/power_off signal and SEQ_LINK signal. The power_on/power_offsignal controls whether the sequencing is in power_on mode for turningon power to multiple devices in a predetermined sequence or power_offmode for turning off power to multiple devices in a reverse sequence.The SEQ_LINK signal controls when the sequence counters, located in eachparticipating device, are allowed to count to the subsequent state.During power supply sequencing it is often necessary to monitor thesupply output after it has been enabled to ensure that it turns on fullybefore sequencing the next supply. Using the open drain SEQ_LINK signal,any device can pull the signal low allowing it to hold-off the sequenceuntil the power supply the particular device is monitoring has turned onor turned off fully. Once this has occurred, the device can let go ofthe SEQ_LINK signal allowing it to return high as long as no otherdevice is pulling it low. The change in the state of the SEQ_LINK signalcauses multiple linked devices to increment or decrement their sequencecounters resulting in a sequenced operation in a coordinated manner.Each sequencing logic circuit of these participating devices responds toa predetermined state of its sequence counter to enable the power on orpower off of the power supply it controls. This predetermined state ofthe sequence counter is called the sequence position.

BRIEF DESCRIPTION OF DRAWINGS

So that the manner in which the above recited features, advantages andobjects of the present invention are attained and can be understood indetail, a more particular description of the invention, brieflysummarized above, may be had by reference to the embodiments thereofwhich are illustrated in the appended drawings.

It is to be noted, however, that the appended drawings illustrate onlytypical embodiments of this invention and are therefore not to beconsidered limiting of its scope, for the present invention may admit toother equally effective embodiments.

FIG. 1 is a diagram illustrating an electronics system wherein thesystem and method of the present invention may advantageously beutilized.

FIG. 2 is a more detailed block diagram of the sequencing logic circuitin a device of a power sequencing system in accordance with anembodiment of the present invention.

FIGS. 3A, 3B, and 3C are timing diagrams of the power sequencing systemin accordance with an embodiment of the present invention.

FIG. 4 is a high level logical flow chart of a method for selectivelycontrolling the power on and power off sequence of an electronics systemin accordance with an embodiment of the present invention.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth toprovide a more thorough understanding of the present invention. However,it will be apparent to one of skill in the art that the presentinvention may be practiced without one or more of these specificdetails. In other instances, well-known features have not been describedin order to avoid obscuring the present invention.

FIG. 1 is a diagram illustrating an electronics system comprising device0, device 1, through device N for enabling and monitoring power supply0, power supply 1, through power supply N via control signalssupply_enable 0, supply_enable 1, through supply_enable N andsupply_voltage 0, supply_voltage 1, through supply_voltage N. Apower_on/power_off signal controls each device to be in a power on modeor a power off mode. Each device drives a SEQ_LINK signal via an opendrain wired-OR circuit.

FIG. 2 is a more detailed block diagram of the sequencing logic circuitin each of the devices in FIG. 1. With the exception of the SEQ_LINK andPOWER_ON/POWER_OFF being global signals in FIG. 1, the rest of thecomponents and signals shown in FIG. 2 are local to each of the devicesin FIG. 1.

A n-BIT COUNTER 201 has a negative edge triggered clock input CLK-drivenby signal SLD1 which is a delayed version of signal SEQ_LINK. The n-BITCOUNTER 201 is configured by the signal POWER_ON/POWER_OFF to eitherincrement or decrement a n-bit CTR[n-1:0] signal responding to thenegative edge of the SLD1 signal.

A DIGITAL COMPARATOR 203 generates a MATCH signal by comparing the n-bitCTR[n-1:0] signal generated by the n-BIT COUNTER to a n-bitCHX_SP[n-1:0] signal generated by PRE-PROGRAMMED n-BIT SEQUENCE POSITION204. The MATCH signal causes a SUPPLY SEQUENCER 205 to generate aSUPPLY_ENABLE signal which enables a power supply associated with theparticular sequencing logic circuit. The PRE-PROGRAMMED n-BIT SEQUENCEPOSITION 204 in each of the devices in FIG. 1 are independentlyconfigured according to a predetermined sequence.

The SUPPLY SEQUENCER 205 monitors the power supply and generates aPOWEER_GOOD signal upon the power supply reaching a stable state afterbeing enabled. The POWEER_GOOD signal and MATCH signal together generatea SEQ_LINK_DISABLE signal which can disable or enable a pulse generatorcircuit 200 composed of NOR gate 206, open drain transistor 207, DELAY1,DELAY2, and SET/RESET circuit 202. All of the pulse generator circuits200 in each of the devices in FIG. 1 are disabled and enabled togetheraccording to the wired-OR operation of the open drain transistorconnection to the global signal SEQ_LINK. While enabled, the pulsegenerator circuit 200 generates a SEQ_LINK signal with pulse high widthequaling DELAY1 approximately and pulse low width equaling DELAY2approximately. At the beginning of the power sequencing operation ineach of the devices in FIG. 1, a HALT signal is deactivated and thepulse generator circuit 200 is enabled, signal SEQ_LINK increments ordecrements the n-BIT COUNTER synchronously and repetitively until aMATCH signal is generated in one or more of the devices in FIG. 1. TheMATCH signal causes the corresponding SUPPLY SEQUENCER 205 to generate aSUPPLY_ENABLE signal and to hold the corresponding POWER_GOOD signal ina low state prior to the corresponding power supply reaching a stablestate after being enabled. The corresponding SEQ_LINK_DISABLE signal areheld active high by the MATCH signal and the corresponding POWER_GOODsignal to disable the corresponding pulse generator circuit 200 with theSEQ_LINK signal being held at a low state. As a result, all of the pulsegenerator circuits 200 in each of the devices in FIG. 1 are disabledaccording to the wired-OR operation of the open drain transistorconnection to the global signal SEQ_LINK. Upon all corresponding powersupplies in each of the devices having a MATCH signal generated reachingstable state, all the corresponding SEQ_LINK_DISABLE signals aredeactivated. As a result, all the pulse generator circuits 200 in eachof the devices in FIG. 1 are again enabled and the n-BIT COUNTER in eachof the devices in FIG. 1 continue to increment or decrement until a nextMATCH signal is generated with another matching sequence position in oneor more of the devices in FIG. 1. Additional power supplies in these oneor more devices are enabled in the same way as described previously. Inthis fashion the SEQ_LINK signal eventually increment or decrement allthe n-BIT COUNTER in each of the devices in FIG. 1 to a terminal statewherein all the power supplies in all devices in FIG. 1 are enabled. AHALT signal is generated at this point to disable all the pulsegenerator circuits in the system. The power sequencing operation iscomplete.

During the power sequencing operation, through the operation of the opendrain wired-OR circuits, all of the pulse generator circuits 200 in eachof the devices in FIG. 1 operate in a coordinated manner to generate theSEQ_LINK with pulse high width equaling DELAY1 approximately and pulselow width equaling DELAY2 approximately as long as none of the deviceshas a MATCH signal generated. Any one of device 0, device 1, throughdevice N having a MATCH signal generated can hold SEQ_LINK signal at alow state and disable all the pulse generator circuits 200 in the systemof FIG. 1.

FIG. 3A is a timing diagram illustrating the operation of a particularsequencing logic circuit in FIG. 2 wherein the n-BIT COUNTER 201 isconfigured by the signal POWER_ON/POWER_OFF to increment in a power onmode. The PRE-PROGRAMMED n-BIT SEQUENCE POSITION 204 is configured to avalue Y in this sequencing logic circuit. The timing diagram illustratesthe timing sequences as the value of the n-bit CTR[n-1:0] signal isincremented from Y−1 through Y+2 by the n-BIT COUNTER 201 in thissequencing logic circuit. The cross hatched portion of CTR[n-1:0]signal, MATCH signal, and SEQ_LINK_DISABLE signal indicate the unstabletransition period of the sequencing logic circuit. DELAY2 period isshown to be longer than the unstable transition period for properoperation of NOR gate 206 in the pulse generator circuit 200. DELAY1 isshown to be of a sufficient time period for proper operation of n-BITCOUNTER 201 as SEQ_LINK signal travels throughout the system in FIG. 1.

FIG. 3B is a timing diagram illustrating the operation of two sequencinglogic circuits of device 0 and device 1 in FIG. 1. The PRE-PROGRAMMEDn-BIT SEQUENCE POSITION 204 is configured to a value Y in the sequencinglogic circuit of device 0. The PRE-PROGRAMMED n-BIT SEQUENCE POSITION204 is configured to a value Y+1 in the sequencing logic circuit ofdevice N.

FIG. 3C is a timing diagram illustrating the operation of two sequencinglogic circuits of device 0 and device 1 in FIG. 1. The PRE-PROGRAMMEDn-BIT SEQUENCE POSITION 204 is configured to a value Y in the sequencinglogic circuit of device 0. The PRE-PROGRAMMED n-BIT SEQUENCE POSITION204 is also configured to a value Y in the sequencing logic circuit ofdevice N.

FIG. 4 is a high level logical flow chart of a method for turning on aplurality of power supplies in a predetermined sequence and turning offthe plurality of power supplies in a reverse sequence. It is shown thatthe counters increment in a power on mode and decrement in a power offmode.

Alternative embodiment 1 includes a configuration wherein the countersdecrement in a power on mode and increment in a power off mode.

Alternative embodiment 2 includes a configuration wherein all the n-BITCOUNTER 201 in each of the devices in FIG. 1 are advancing synchronouslybut with different initial states.

Alternative embodiment 3 includes a configuration wherein multipledevices can be on a physical module and multiple sequencing logiccircuits can be combined to share common components.

Alternative embodiment 4 includes a configuration wherein the sequenceposition configured for a power on mode is different from the sequenceposition configured for a power off mode.

Alternative embodiment 5 includes a configuration wherein one or more ofthe devices of FIG. 1 enable and monitor electronic components otherthan power supplies.

Foregoing described embodiments of the invention are provided asillustrations and descriptions. They are not intended to limit theinvention to precise form described. In particular, it is contemplatedthat functional implementation of invention described herein may beimplemented equivalently in hardware, software, firmware, and/or otheravailable functional components or building blocks, and that connectionsor networks may be wired, wireless, or a combination of wired andwireless. Other variations and embodiments are possible in light ofabove teachings, and it is thus intended that the scope of invention notbe limited by this Detailed Description, but rather by Claims following.

1. An apparatus for enabling a plurality of power supplies, theapparatus comprises: a SEQ_LINK signal; and a plurality of controllers,each configured with a predetermined sequence position; wherein eachcontroller is responsive to the SEQ_LINK signal for enabling a powersupply according to the predetermined sequence position.
 2. TheApparatus of claim 1 wherein each controller comprises: a countercircuit; a comparator circuit wherein a match signal is determined fromcomparing a first state of the counter circuit to the predeterminedsequence position; a logic circuit responsive to the match signal forenabling the power supply and detecting a stable state of the powersupply after an enabling event; and a pulse generator circuit; whereinthe SEQ_LINK signal is in operational communication with each controllerresponsive to each pulse generator circuit; wherein the SEQ_LINK signalis in operational communication with each controller for advancing eachcounter circuit.
 3. The apparatus of claim 2, wherein the SEQ_LINKsignal continues to advance each counter circuit synchronously andrepetitively to a subsequent state until a match signals is determinedin one or more controllers.
 4. The apparatus of claim 3, wherein theSEQ_LINK signal is disabled upon the match signal being determined untilupon the stable state of the power supply being detected.
 5. Theapparatus of claim 4, wherein a first delay period of a firstpredetermined duration is initiated by the pulse generator circuit upondetermining the stable state of the power supply after the enablingevent, wherein the SEQ_LINK signal initiates each counter circuit toadvance to the subsequent state following the first delay period.
 6. Theapparatus of claim 5, wherein a second delay period of a secondpredetermined duration is initiated by the pulse generator circuitfollowing the initiation of the advance of the counter circuit to thesubsequent state, wherein the SEQ_LINK signal is disabled during thesecond delay period, and wherein the SEQ_LINK signal is further disabledfollowing the match signal being determined until upon the stable stateof the power supply being detected.
 7. The apparatus of claim 6 whereinthe SEQ_LINK signal is connected to an open drain wired-OR circuit witha pull-up resistor tied to a common open drain node. The wired-ORcircuit is driven by the pulse generator circuit of each controller. 8.The apparatus of claim 1 wherein each of the plurality of power suppliesis turned on upon being enabled.
 9. The apparatus of claim 1 whereineach of the plurality of power supplies is turned off upon beingenabled.
 10. The apparatus of claim 2 further comprising a counterdirection circuit, wherein one state of the counter direction circuitcauses each counter circuit to increment upon being advanced and eachpower supply to be turned on upon being enabled, and wherein anotherstate of the counter direction circuit causes each counter circuit todecrement upon being advanced and each power supply to be turned offupon being enabled.
 11. The apparatus of claim 1 wherein the SEQ_LINKsignal is initiated by a processor.
 12. A method for turning on aplurality of power supplies in a predetermined sequence and turning offthe plurality of power supplies in a reverse sequence, the methodcomprising the steps of: assigning a sequence position to each powersupply; providing a counter circuit for each power supply; verifying acounter direction circuit to be in an on state; initializing all countercircuits to a first state; incrementing all counter circuitssynchronously and repetitively to a subsequent state until thesubsequent state matches a sequence position assigned to one or morepower supplies; turning on one or more power supplies assigned with thematching sequence position; waiting for all power supplies assigned withthe matching sequence position to reach a stable state; continuing toincrement all counter circuits and to turn on one or more power suppliesuntil all of the plurality of power supplies are turned on and allcounter circuits are incremented to a second state; verifying thecounter direction circuit to be switched to an off state; decrementingall counter circuits synchronously and repetitively to a subsequentstate until the subsequent state matches a sequence position assigned toone or more power supplies; turning off one or more power suppliesassigned with the matching sequence position; waiting for all powersupplies assigned with the matching sequence position to reach a stablestate; continuing to decrement all counter circuits and to turn off oneor more power supplies until all of the plurality of power supplies areturned off and all counter circuits are decremented to the first state.